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february 2007 rev 4 1/36 1 stm1404 3v fips-140 security supervisor with battery switchover features stm1404 supports fips-140 security level 4 ? four high-impedance physical tamper inputs ? over/under operating voltage detector ? security alarm (sal ) on tamper detection ? over/under operating temperature detector ? over/under temperature thresholds are customer-selectable and factory- programmed supervisory functions ? automatic battery switchover ?rst output (open drain) ? manual (push-button) reset input (mr ) ? power-fail comparator (pfi/pfo ) vccsw (v cc switch output) ? low when switched to v cc ? high when switched to v bat (batt on indicator) battery low voltage detector (power-up) optional v ref (1.237v) ? (available for stm1404a only) low battery supply current (5.3a typ) secure low profile 16-pin, 3x3mm, qfn package rohs compliance ? lead-free components compliant with the rohs directive qfn16, 3x3mm (q) table 1. device options supervisory functions (1) physical tamper inputs over/under voltage alarms over/under temperature alarms v ref (1.237v) option v out status, during alarm vccsw status, during alarm stm1404a ??? ? ? on normal mode (2) stm1404b (3) ??? ? note (4) high-z high stm1404c ??? ? note (4) ground high 1. sal , rst , pfo , and bld are open drain. 2. normal mode: low when v out is internally switched to v cc and high when v out is internally switched to battery. 3. contact local st sales office for availability. 4. pin 9 is the v ref pin for stm1404a. it is the v tpu pin for stm1404b/c. www.st.com
contents stm1404 2/36 contents summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 v out pin modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 stm1404a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 stm1404b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 stm1404c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 sal, security alarm output (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 tp 1 , tp 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 tp 2 , tp 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 vccsw, v cc switch output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 bld, v bat low voltage detect output (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . 13 active-low rst output (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 mr, manual reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 pfo, power-fail output (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 pfi, power-fail input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 v ref , reference voltage output (1.237, typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 v out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 v tpu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 v cc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 v bat. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 push-button reset input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 back-up battery switchover. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 negative-going v cc transients and undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . 17 tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 physical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
stm1404 contents 3/36 typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
list of tables stm1404 4/36 list of tables table 1. device options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. i/o status in battery back-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 5. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 6. dc and ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 7. physical and environmental tamper detection levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 8. qfn16 ? 16-lead, quad, flat package, no lead, 3x3mm body size mechanical data . . . . . 32 table 9. ordering information scheme (see figure 31 on page 34 for marking information) . . . . . . 33 table 10. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
stm1404 list of figures 5/36 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. qfn16 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. tamper pin (tp 1 or tp 3 ) normally high (nh) external hookup (switch closed). . . . . . . . . 10 figure 6. tamper pin (tp 1 or tp 3 ) normally high (nh) external hookup (switch open) . . . . . . . . . . 10 figure 7. tamper pin (tp 2 or tp 4 ) normally low (nl) external hookup (switch closed) . . . . . . . . . 10 figure 8. tamper pin (tp 2 or tp 4 ) normally low (nl) external hookup (switch open). . . . . . . . . . . 11 figure 9. power-fail comparator waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 10. supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 11. v bat -to-v out on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 12. supply current vs. temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 figure 13. v pfi threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 14. reset comparator propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 15. power-up t rec vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 16. normalized reset threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 17. pfi to pfo propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 18. rst output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 19. rst response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 20. power-fail comparator response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 21. power-fail comparator response time (de-assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 22. v cc to reset propagation delay vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 23. maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 24. ac testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 25. mr timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 26. stm1404 switchover diagram, condition a (v bat < v sw ) . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 27. stm1404 switchover diagram, condition b (v bat > v sw ) . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 28. temperature hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 29. qfn16 ? 16-lead, quad, flat package, no lead, 3x3mm body size, outline . . . . . . . . . . . . 31 figure 30. qfn16 ? 16-lead, quad, flat package, no lead, 3x3mm, recommended footprint . . . . . . . 32 figure 31. topside marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
summary description stm1404 6/36 summary description the stm1404 family of security supervisors ar e a low power family of intrusion (tamper) detection chips targeted at manufacturers of pos terminals and other systems, to enable them to meet physical and/or environmental intrusion monitoring requirements as mandated by various standards, such as federal information processing standards (fips) pub 140 entitled ?security requirements for cryptographic modules,? published by the national institute of standards and technology, u.s. department of commerce), emvco, iso, zka, and visa ped. stm1404 will target the highest security level 4 and include both physical and environmental (voltage and temperature) monitoring. the stm1404 include automatic battery switchover, rst output (open drain), manual (push-button) reset input (mr ), power-fail comparator (pfi/pfo ), physical and/or environmental tamper detect/security alarm, and battery low voltage detect features. the stm1404a also offers a v ref (1.237v) as an option on pin 9. on stm1404b/c this pin is v tpu (internally switched v cc or v bat ). v out pin modes the stm1404 is available in three versions, corresponding to three modes of the v out pin (supply voltage out), when the sal (security alarm) is asserted (active-low) upon tamper detection: stm1404a v out stays on (at v cc or v bat ) when sal is driven low (activated). stm1404b v out is set to high-z when sal is driven low (activated). stm1404c v out is driven to ground when sal is activated (may be used when v out is connected directly to the v cc pin of the external sram that holds the cryptographic codes). all variants (see table 1: device options ) are pin-compatible and available in a security- friendly, low profile, 16-pin qfn package.
stm1404 summary description 7/36 figure 1. logic diagram 1. v ref only for stm1404a; v tpu for stm1404b/c. 2. normal mode: low when v out is internally switched to v cc and high when v out is internally switched to battery. 3. sal , rst , pfo , and bld are open drain. note: see section : pin descriptions on page 12 for details. table 2. signal names vccsw (1) 1. normal mode: low when v out is internally switched to v cc and high when v out is internally switched to battery. v cc switch output mr manual (push-button) reset input pfi power-fail input tp 1 - tp 4 independent physical tamper detect pins 1 through 4 v out supply voltage output rst (2) 2. sal , rst , pfo , and bld are open drain. active-low reset output pfo (2) power-fail output sal (2) security alarm output bld (2) battery low voltage detect v ref (3) 3. v ref only for stm1404a; v tpu for stm1404b/c. 1.237v reference voltage v tpu (3) tamper pull-up (v cc or v bat ) v bat back-up supply voltage v cc supply voltage v ss ground ai09682a v cc v bat stm1404 v ss v out v ref or v tpu (1) v ccsw (2) mr sal (3) bld (3) pfi tp 1 (nh) tp 2 (nl) tp 3 (nh) tp 4 (nl) pfo (3) rst (3)
summary description stm1404 8/36 figure 2. qfn16 connections note: see section : pin descriptions on page 12 for details. 1. normal mode: low when v out is internally switched to v cc and high when v out is internally switched to battery. 2. sal , rst , pfo , and bld are open drain. 3. v ref only for stm1404a; v tpu for stm1404b/c. figure 3. block diagram 1. required for battery-reve rse charging protection. 2. user supplied. 3. open drain. 4. v ref only for stm1404a; v tpu for stm1404b/c. 1 pfo (2) pfi tp 1 (nh) bld (2) mr rst (2) v cc v ccsw (1) v out v ref or v tpu (3) v bat v ss ai09683 2 3 4 8 7 6 5 sal (2) 9 10 11 12 13 14 15 16 tp 2 (nl) tp 3 (nh) tp 4 (nl) ai09684a compare @ power-up v rst v int v out v ref (4) 1.237v v ref generator compare compare compare compare compare high temp. sense t a > t h low temp. sense t a < t l t rec generator v pfi v bat (2) v det v hv v lv v so v cc pfi tp 1 (nh) tp 2 (nl) tp 3 (nh) tp 4 (nl) mr rst (3) pfo (3) bld (3) v ccsw sal (3) v tpu (4) bat54j (1)
stm1404 summary description 9/36 figure 4. hardware hookup 1. normal mode: low when v out is internally switched to v cc and high when v out is internally switched to battery. 2. capacitor (c) is typically 10f. 3. open drain 4. diode is required for battery reverse charge protection. 5. v ref only for stm1404a; v tpu for stm1404b/c. v cc ai09690a v cc mr v out v ref (5) or v tpu v ccsw (1) v cc lpsram pfi c (2) 0.1 f 1.0 f stm1404 pfo (3) rst (3) bld (3) to microprocessor reset unregulated voltage regulator v cc v in r1 r2 push-button from actuator device (e.g., switches, wire mesh) bat54j (4) v bat tp 1 tp 2 tp 3 tp 4 to microprocessor nmi to microprocessor sal (3) to physical tamper pins tp x to adc
summary description stm1404 10/36 figure 5. tamper pin (tp 1 or tp 3 ) normally high (nh) external hookup (switch closed) 1. r typical is 10m . resistors must be protected against conductive materials. figure 6. tamper pin (tp 1 or tp 3 ) normally high (nh) external hookup (switch open) 1. r typical is 10m . resistors must be protected against conductive materials. figure 7. tamper pin (tp 2 or tp 4 ) normally low (nl) external hookup (switch closed) 1. r typical is 10m . resistors must be protected against conductive materials. ai09698a v out (stm1404a) or v tpu (stm1404b/c) r (1) switch normally closed; tamper detection on open tp 1 or tp 3 ai10461a v out (stm1404a) or v tpu (stm1404b/c) r (1) switch normally open tamper detection when closed tp 1 or tp 3 ai09699a v out (stm1404a) or v tpu (stm1404b/c) r (1) switch normally closed; tamper detection on open tp 2 or tp 4
stm1404 summary description 11/36 figure 8. tamper pin (tp 2 or tp 4 ) normally low (nl) external hookup (switch open) 1. r typical is 10m . resistors must be protected against conductive materials. ai10462a v out (stm1404a) or v tpu (stm1404b/c) r (1) switch normally open; tamper detection when closed tp 2 or tp 4
pin descriptions stm1404 12/36 pin descriptions see figure 1: logic diagram and table 2: signal names for a brief overview of the signals connected to this device. sal , security alarm output (open drain) this signal can be generated when any of the following conditions occur: v int > v hv , where v hv = upper voltage trip limit (4.2v typ); and where v int = v cc or v bat ; v int < v lv , where v lv = lower voltage trip limit (2.0v typ); and where v int = v cc or v bat ; or when any of the physical tamper inputs, tp 1 to tp 4 , change from their normal states to the opposite (i.e., intrusion of a physical enclosure). t a > t h , where t h is an upper temperature trip limit specified by the customer (+80c, +85c, and +95c), factory-programmed (stm1404 only); t a < t l , where t l is a lower temperature trip limit specified by the customer (?25c or ?35c), factory-programmed (stm1404 only); note: 1 the default state of the sal output during initial power-up is undetermined. 2 the alarm function will operate either with v cc on or when the part is internally switched from v cc to v bat . tp 1 , tp 3 physical tamper detect pin set normally to high (nh). they are connected externally through a closed switch or a high-impedance resistor to v out (in the case of stm1404a) or v tpu (in the case of stm1404b/c. a tamper cond ition will be detected when the input pin is pulled low (see figure 5 and figure 6 on page 10 ). if not used, tie the pin to v out (for stm1404a) or v tpu (for stm1404b/c). tp 2 , tp 4 physical tamper detect pin set normally to low (nl). they are connected externally through a high-impedance resistor or a closed switch to v ss . a tamper condition will be detected when the input pin is pulled high (see figure 7 and figure 8 on page 11 ). if not used, tie the pin to v ss . vccsw , v cc switch output this output is low when v out (see section : v out on page 14 ) is internally switched to v cc ; in this mode it may be used to turn on an external p-channel mosfet switch which can source an external de vice directly from v cc for currents greater than 80ma (bypassing the stm1404). this pin goes high when v out is internally switched to v bat and may be used as a ?battery on? indicator.
stm1404 pin descriptions 13/36 if a security alarm (sal ) is issued on tamper, then the state of the vccsw pin is as follows: 1. stm1404a (v out remains on when sal is active-low): vccsw pin will continue to operate in normal mode; 2. stm1404b (v out is taken to high-z when sal is active-low): vccsw pin will be set to high when this occurs; and 3. stm1404c (v out is driven to ground when sal is active-low): vccsw pin will be set to high when this occurs. bld , v bat low voltage detect output (open drain) this is an internally loaded test of the battery, activated only during a power-up sequence to insure that the battery is good either prior to or after encapsulation of the module. there are three customer options for v det : 2.3v (2.5v ? external diode drop of about 0.2v) for a 3v lithium cell; 2.5v (2.7v ? 0.2v) for a 3v lithium cell; or 3.2v (3.4v ? 0.2v) for a 3.68v lithium ?aa? battery. this output pin will go active-low when it detects a voltage on the v bat pin below v det . bld will be released when v cc drops below v rst . active-low rst output (open drain) goes low and stays low when v cc drops below v rst (reset threshold selected by the customer), or when mr is logic low. it remains low for t rec (200ms, typical) after v cc rises above v rst and mr goes from low to high. mr , manual reset input a logic low on mr asserts the rst output. the rst output remains asserted as long as mr is low and for t rec after mr returns to high. this active low input has an internal 40k (typical) pull-up resistor. it can be driven from a ttl or cmos logic line or shorted to ground with a switch. leave it open if unused. pfo , power-fail output (open drain) when pfi is less than v pfi (power-fail input threshold voltage) or v cc falls below v sw (battery switchover threshold ~ 2.4v), pfo goes low, otherwise, pfo remains high. leave this pin open if unused. pfi, power-fail input when pfi is less than v pfi , or when v cc falls below v sw (see pfo , above), pfo goes active-low. if this function is unused, connect this pin to v ss . v ref , reference voltage output (1.237, typ) this is valid only when v cc is between 2.4v and 3.6v. when v cc falls below 2.4v (v sw ), v ref is pulled to ground with an internal 100k resistor. this is an optional feature available on the stm1404a. on the stm1404b/c, this pin is v tpu (internally switched v cc or v bat ). if unused, this pin should float.
pin descriptions stm1404 14/36 v out this is the supply voltage output. when v cc rises above v so (battery backup switchover voltage), v out is supplied from v cc . in this condition, v out may be connected externally to v cc through a p-channel mosfet switch. when v cc falls below the lower value of v sw (~2.4v), or v bat , v out is supplied from v bat . it is recommended that the v out pin be connected externally to a capacitor that will reta in a charge for a period of time, in case an intruder forces v cc or v bat to ground. the rectifying diode connected from the positive terminal of the battery to the v bat pin of the stm1404 will prevent discharge of the capacitor. three variations of parts will be offered with the following options: 1. stm1404a: v out remains on when sal is active-low; vccsw pin will continue to operate in normal mode (see section : vccsw, v cc switch output on page 12 ); 2. stm1404b: v out is taken to high-z when sal is active-low; vccsw pin will be set to high when this occurs; and 3. stm1404c: v out is driven to ground when sal is active-low; vccsw pin will be set to high when this occurs. v tpu for stm1404b and stm1404c, this pin provides pull-up voltage for the physical tamper pins (tp1-4). this pin is not to be used as voltage supply source for any other purpose. note: v tpu is the internally switched supply voltage from either the v cc pin or the v bat pin. v cc this is the supply vo ltage (2.2v to 3.6v). v bat this is the secondary (backup battery) supply voltage. the pin is connected to the positive terminal of the battery with a rectifying diode like the bat54j from stmicroelectronics for reverse charge protection. voltage at this pin, after diode rectificat ion, will be approximately 0.2v less than the battery voltag e, and will depend on the type of battery used as well as the i bat being drawn. (a capacitor of at least 1.0f connected between the v bat pin and v ss is required.) if no battery is used, connect the v bat pin to the v cc pin. v ss ground, v ss , is the reference for the power supply. it must be connected to system ground.
stm1404 operation 15/36 operation reset input the stm1404 security supervisor asserts a reset signal to the mcu whenever v cc goes below the reset threshold (v rst ), or when the push-button reset input (mr ) is taken low. rst is guaranteed to be a logic low for 0v < v cc < v rst if v bat is greater than 1v. without a back-up battery, rst is guaranteed valid down to v cc =1v. during power-up, once v cc exceeds the reset threshold an internal timer keeps rst low for the reset time-out period, t rec . after this interval rst returns high. if v cc drops below the reset threshold, rst goes low. each time rst is asserted, it stays low for at least the reset time-out period (t rec ). any time v cc goes below the reset threshold the internal timer clears. the reset timer starts when v cc returns above the reset threshold. push-button reset input a logic low on mr asserts reset. reset remains asserted while mr is low, and for t rec (see figure 25 on page 25 ) after it returns high. the mr input has an internal 40k pull-up resistor, allowing it to be left open if not used. this input can be driven with ttl/cmos-logic levels or with open-drain/collector outputs. connect a normally open momentary switch from mr to ground to create a manual reset function; external debounce circuitry is not required. if mr is driven from long cables or the device is used in a noisy environment, connect a 0.1f capacitor from mr to v ss to provide additional noise immunity. mr may float, or be tied to v cc when not used. back-up battery switchover in the event of a power failure, it may be necessary to preserve the contents of external sram through v out . with a backup battery installed with voltage v bat , the devices automatically switch the sram to the back-up supply when v cc falls. note: if back-up battery is not used, connect both v bat and v out to v cc . this family of security supervisors does not always connect v bat to v out when v bat is greater than v cc . v bat connects to v out (through a 100 switch) when v cc is below v sw (~2.4v) or v bat (whichever is lower). this is done to allow the back-up battery (e.g., a 3.6v battery) to have a higher voltage than v cc . assuming that v bat > 2.0v, switchover at v so ensures that battery back-up mode is entered before v out gets too close to the 2.0v minimum required to reliably retain data in most external srams. when v cc recovers, hysteresis is used to avoid oscillation around the v so point. v out is connected to v cc through a 3 pmos power switch. note: the back-up battery may be removed while v cc is valid, assuming v bat is adequately decoupled (0.1f typ), without danger of triggering a reset.
operation stm1404 16/36 the power-fail input (pfi) is compared to an internal reference voltage (independent from the v rst comparator). if pfi is less than the power-fail threshold (v pfi ), the power-fail output (pfo ) will go low. this function is intended for use as an underv oltage detector to signal a failing power supply. typically pfi is connected through an external voltage divider (see figure 4 on page 9 ) to either the unregulated dc input (if it is available) or the regulated output of the v cc regulator. the voltage divider can be set up such that the voltage at pfi falls below v pfi several milliseconds be fore the regulated v cc input to the stm1404 or the microprocessor drops below the minimum operating voltage. during battery back-up, the power-fail comparator is turned off and pfo goes (or remains) low (see figure 9 on page 17 ). this occurs after v cc drops below v sw (~2.4v). when power returns, the power-fail comparator is enabled and pfo follows pfi. if the comparator is unused, pfi should be connected to v ss and pfo left unconnected. pfo may be connected to mr so that a low voltage on pf i will generate a reset output. applications information these supervisor circuits are not short-circuit protected. shorting v out to ground - excluding power-up transients such as charging a decoupling capacitor - destroys the device. decouple both v cc and v bat pins to ground by placing 0.1f capacitors as close to the device as possible. table 3. i/o status in battery back-up pin status v out connected to v bat through internal switch v cc disconnected from v out pfi disabled pfo logic low mr disabled rst logic low v bat connected to v out vccsw logic high v ref pulled to v ss below 2.4v (v sw ) bld logic high v tpu connected to v bat through an internal switch
stm1404 operation 17/36 figure 9. power-fail comparator waveform negative-going v cc transients and undershoot the stm1404 devices are relatively immune to negative-going v cc transients (glitches). figure 23 on page 23 was generated using a negative pulse applied to v cc , starting at v rst + 0.3v and ending below the reset threshold by the magnitude indicated (comparator overdrive). the graph indicates the maximum pulse width a negative v cc transient can have without causing a reset pulse. as the magnitude of the transient increases (further below the threshold), the maximum allowable pulse width decreases. any combination of duration and overdrive which lies under the curve will no t generate a reset signal. typically, a v cc transient that goes 100mv below the reset th reshold and lasts 40s or less will not cause a reset pulse. a 0.1f bypass capacitor mounted as close as possible to the v cc pin provides additional transient immunity (see figure 10 ). in addition to transients that are caused by normal sram operation, power cycling can generate negative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, stmicroelectronics recommends connecting a schottky diode from v cc to v ss (cathode connected to v cc , anode to v ss ). schottky diode 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface mount. figure 10. supply voltage protection ai08861a v cc v rst v sw (2.4v) trec rst pfo pfo follows pfi pfo follows pfi ai02169 v cc 0.1 f device v cc v ss
tamper detection stm1404 18/36 tamper detection physical there are four (4) high-impedance physical tamper detect input pins, 2 normally set to high (nh) and 2 normally set to low (nl). each input is designed with a glitch immunity (see table 7 on page 30 ). these inputs can be connected externally to several types of actuator devices (e.g., switches, wire mesh). a tamper on any one of the four inputs that causes its state to change will trigger the security alarm (sal ) and drive it to active-low. once the tamper condition no longer exists, the sal will return to its normal high state. tp 1 and tp 3 are set normally to high (nh). they are connected externally through a closed switch or a high-impedance resistor to v out (in the case of stm1404a or stm1404a) or v tpu (in the case of stm1404b/c), a tamper co ndition will be detected when the input pin is pulled low (see figure 5 and figure 6 on page 10 ). if not used, tie the pin to v out or v tpu . tp 2 and tp 4 are set normally to low (nl). they are connected externally through a high- impedance resistor or a closed switch to v ss . a tamper condition will be detected when the input pin is pulled high (see figure 7 and figure 8 on page 11 ). if not used, tie the pin to v ss . supply voltage the internally switched supply voltage, v int (either v cc input or v bat input) is continuously monitored. if v int should exceed the over voltage trip point, v hv (set at 4.2v, typical), or should go below the under voltage trip point, v lv (set at 2.0v, typical). sal will be driven active-low. once the tamper condition no longer exists, the sal pin will return to its normal high state. temperature the stm1404 has a built-in, bandgap-based sensor to monitor the temperature. if a preset (customer-selectable, factory-programmed) over-temperature trip point (t h ) or under- temperature trip point (t l ) is exceeded, the sal is asserted low. when no tamper condition exists, sal is normally high (see section : pin descriptions on page 12 ). when a tamper is detected, the sal is activated (driven low), independent of the part type. v out can be driven to one of three states, depending on which variant of stm1404 is being used (see table 1 on page 1 ): on; high-z; or ground (v ss ). note: the stm1404 must be initially powered above v rst to enable the tamper detection alarms. for example, if the battery is on while v cc = 0v, no alarm condition can be detected until v cc rises above v rst (and t rec expires). from this point on, alarms can be detected either on battery or v cc . this is done to avoid false alarms when the device goes from no power to its operational state.
stm1404 typical operating characteristics 19/36 typical operating characteristics note: typical values are at t a = 25c. figure 11. v bat -to-v out on-resistance vs. temperature figure 12. supply current vs. temperature (no load) 100 120 140 160 180 200 220 ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature [ c] v bat - to - v out on-resistance [ ] v bat = 2v v bat = 3v v bat = 3.3v v cc = 0v ai09691 0 5 10 15 20 25 30 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 temperature [ c] supply current [a] 2.5v 3.3v 3.6v ai09692
typical operating characteristics stm1404 20/36 figure 13. v pfi threshold vs. temperature figure 14. reset comparator propagation delay vs. temperature figure 15. power-up t rec vs. temperature figure 16. normalized reset threshold vs. temperature 1.225 1.230 1.235 1.240 1.245 1.250 1.255 ?50 ?30 ?10 10 30 50 70 90 110 130 temperature [ c] v pfi threshold [v] v cc = 2.5v v cc = 3.3v v bat = 3.0v ai09693 10 12 14 16 18 20 22 24 ?60 ?40 ?20 0 20 40 60 80 100 temperature [ c] propagation delay [s] v bat = 3.0v 100mv overdrive ai09143 195 200 205 210 215 ?50 ?30 ?10 10 30 50 70 90 110 130 temperature [ c] t rec [ms] 10 12 14 16 18 20 22 24 ?60 ?40 ?20 0 20 40 60 80 100 temperature [ c] propagation delay [s] v bat = 3.0v 100mv overdrive ai09143 0.994 0.996 0.998 1.000 1.002 ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature [ c] normalized reset threshold [v] v bat = 3.0v ai09145
stm1404 typical operating characteristics 21/36 figure 17. pfi to pfo propagation delay vs. temperature figure 18. rst output voltage vs. supply voltage figure 19. rst response time (assertion) 0 1 2 3 4 5 6 7 8 9 ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature [ c] propagation delay [s] ai09148 rst output voltage [v] 500 ms/div ai09149b 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v cc v rst v cc level [v] ai09151b 2 s/div 0.0 1.0 2.0 3.0 4.0 v cc v rst
typical operating characteristics stm1404 22/36 figure 20. power-fail comparator response time (assertion) figure 21. power-fail comparator response time (de-assertion) v pfo level [v] v pfi level [v] 2s/div ai09153b 0.0 1.0 2.0 3.0 4.0 1.15 1.20 1.25 1.30 1.35 1.40 1.45 pfo pfi v pfo level (v) v pfi level (v) 2 s/div ai09154 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 1.15 1.20 1.25 1.30 1.35 1.40 1.45 pfi pfo
stm1404 typical operating characteristics 23/36 figure 22. v cc to reset propagation delay vs. temperature figure 23. maximum transient duration vs. reset threshold overdrive 0 10 20 30 40 50 60 ?60 ?40 ?20 0 20 40 60 80 100 temperature [ c] propagation delay [s] 10v/ms 1v/ms 0.25v/ms ai09155 0 50 100 150 200 250 1 10 100 1000 10000 reset comparator overdrive, v rst ? v cc [mv] transient duration [s] ai09156
maximum rating stm1404 24/36 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 4. absolute maximum ratings symbol parameter value unit t stg storage temperature (v cc off, v bat off) ?55 to 150 c t sld (1) 1. reflow at peak temperature of 255c to 260c for < 30 seconds (total thermal budget not to exceed 180c for between 90 to 150 seconds). lead solder temperature for 10 seconds 260 c v io input or output voltage ?0.3 to v cc +0.3 v v cc /v bat supply voltage ?0.3 to 4.5 v i o output current 20 ma p d power dissipation 320 mw
stm1404 dc and ac parameters 25/36 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 5: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. figure 24. ac testing input/output waveforms figure 25. mr timing waveform table 5. operating and ac measurement conditions parameter stm1404 unit v cc /v bat supply voltage 2.2 to 3.6 v ambient operating temperature (t a )?40 to 85c input rise and fall times 5ns input pulse voltages 0.2 to 0.8v cc v input and output timing ref. voltages 0.3 to 0.7v cc v ai02568 0.8v cc 0.2v cc 0.7v cc 0.3v cc ai09694 rst mr tmlrl trec tmlmh
dc and ac parameters stm1404 26/36 figure 26. stm1404 switchover diagram, condition a (v bat < v sw ) figure 27. stm1404 switchover diagram, condition b (v bat > v sw ) ai10463 v cc = 3.3v v sw = 2.4v v bat v bat ? 75mv v bat ? 35mv v rst v out ai10464 v cc = 3.3v v sw = 2.4v v bat v sw + 40mv v out table 6. dc and ac characteristics sym alter- native description test condition (1) min typ max unit v cc , v bat (2) operating voltage t a = ?40 to +85c 2.2 3.6 v i cc v cc supply current (stm1404a) typ @ 3.3v, 25c 50 65 a v cc supply current (stm1404b,c) 35 50 a v cc supply current in battery back-up mode excluding i out (v bat = 2.3v, v cc = 2.0v, mr = v cc ) 25 35 a i bat (3) v bat supply current in battery back-up mode excluding i out (v bat = 3.6v) 5.3 8.0 a v out1 v out voltage (active) i out1 = 5ma (4) (v cc > v sw ) v cc ? 0.03 v cc ? 0.015 v i out1 = 80ma (v cc > v sw ) v cc ? 0.3 v cc ? 0.15 v i out1 = 250a, v cc > v sw (4) v cc ? 0.0015 v cc ? 0.0006 v v out2 v out voltage (battery back-up) i out2 = 250a, v bat = 2.2v v bat ? 0.1 v bat ? 0.04 v i out2 = 1ma, v bat = 2.2v v bat ? 0.16 v v tpu1 internal switched supply voltage (active) i source = 5ma (v cc > v sw ) v cc ? 0.3 v
stm1404 dc and ac parameters 27/36 v tpu2 internal switched supply voltage (battery back-up) i source = 1ma (v bat = 2.2v) v bat ? 0.10 v i li input leakage current (mr ) mr = 0v; v cc = 3v 20 75 350 a input leakage current (pfi) 0v = v in = v cc ?25 2 +25 na input leakage current (tp1-tp4) 0v = v in = v cc ?1 +1 a i lo output leakage current 0v = v in = v cc (5) ?1 +1 a v ih input high voltage (mr ) v rst (max) < v cc < 3.6v 0.7v cc v v il input low voltage (mr )0.3v cc v v ol output low voltage (pfo , rst , vccsw , sal , bld ) v cc = v rst (max), i sink = 3.2ma 0.3 v v ol output low voltage (rst ) i ol = 40a; v cc = 1.0v; v bat = v cc ; t a = 0c to 85c 0.3 v i ol = 200a; v cc = 1.2v; v bat = v cc 0.3 v table 6. dc and ac characteristics (continued) sym alter- native description test condition (1) min typ max unit
dc and ac parameters stm1404 28/36 v ohb v oh battery back-up (v ccsw ) i source = 100a, 0.8v bat v pull-up supply voltage (open drain) rst , sal , bld , pfo 3.6 v power-fail comparator v pfi pfi input threshold pfi falling (v cc < 3.6v) 1.212 1.237 1.262 v pfi hysteresis pfi rising (v cc < 3.6v) 10 20 mv t pfd pfi to pfo propagation delay 2s battery switchover v so battery back-up switchover voltage (6)(7) power- down v bat > v sw v sw v v bat < v sw v bat v power-up v bat > v sw v sw v v bat < v sw v bat v v sw 2.4 v hysteresis 40 mv battery low voltage detect v det battery detect threshold on power- up only m 2.25 2.30 2.34 v n 2.45 2.50 2.55 v o 3.14 3.20 3.26 v voltage reference (option for stm1404a) (8) v ref voltage reference (see section : v ref , reference voltage output (1.237, typ) on page 13 ) 0c to 85c 1.212 1.237 1.262 v ?40 to 0c 1.200 1.237 1.274 v i ref+ source current 0c to 85c 15 25 a ?40 to 0c 10 15 a i ref? sink current 10 13 a v n output voltage noise f = 100hz to 100kh 10-100 v rm s table 6. dc and ac characteristics (continued) sym alter- native description test condition (1) min typ max unit
stm1404 dc and ac parameters 29/36 reset thresholds v rst (9) reset threshold t v cc falling 3.00 3.075 3.15 v v cc rising 3.00 3.085 3.17 v s v cc falling 2.85 2.925 3.00 v v cc rising 2.85 2.935 3.02 v r v cc falling 2.55 2.625 2.70 v v cc rising 2.55 2.635 2.72 v t rec rst pulse width 140 200 280 ms push-button reset input t mlmh t mr mr pulse width 100 ns t mlrl t mrd mr to rst output delay 60 500 ns 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = v rst (max) to 3.6v; and v bat = 2.8v (except where noted); typical values are for 3.3v and 25c. 2. v cc supply current, logic input leakage, push-button reset functionality, pfi functionality, state of rst tested at v bat = 3.6v, and v cc = 3.6v. the state of rst and pfo is tested at v cc = v cc (min). v bat is voltage measured at the pin. 3. tested at v bat = 3.6v, and v cc = 0v. 4. guaranteed by design. 5. the leakage current measured on the rst , sal , pfo , and bld pins are tested with the output not asserted (output high impedance). 6. when v bat > v cc > v sw , v out remains connected to v cc until v cc drops below v sw . 7. when v sw > v cc > v bat , v out remains connected to v cc until v cc drops below the battery voltage (v bat ) ? 75mv. 8. maximum external capacitive load on v ref pin cannot exceed 1nf. 9. the reset threshold tolerance is wider for v cc rising than for v cc falling due to the 10mv (typ) hysteresis, which prevents internal oscillation. table 6. dc and ac characteristics (continued) sym alter- native description test condition (1) min typ max unit
dc and ac parameters stm1404 30/36 figure 28. temperature hysteresis table 7. physical and environmental tamper detection levels sym parameter test conditions (1) min typ max unit v hv over voltage trip level 4.0 4.2 4.4 v v lv under voltage trip level 1.9 2.0 2.1 v sal propagation delay time (after over/under voltage detection) v hv + 200mv or v lv ? 200mv 25 40 s v htp trip point for nh physical tamper input pins (tp 1 or tp 3 ) v out - 1.3 (2) v out - 0.3 (2) v v lt p trip point for nl physical tamper input pins (tp 2 or tp 4 ) 0.3 1.0 v sal propagation delay time (3) (after physical tamper pin detection) v htp = v out /v tpu ; v lt p = v ss v dd = 3.6 30 50 s physical tamper input (tp x ) glitch immunity 15 s t h factory-programmed i out = 0ma ?5 80, 85, 95 +5 c t l ?5 ?25, ?35 +5 c t hyst temperature hysteresis 10 c 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = v lv to v hv (except where noted). all physical and environmental tamper functions are operational across the full te mperature alarm range for stm1404. 2. in the case of stm1404a, physical tamper input pins (tp x ) are referenced to v out (pin 12). in the case of stm1404b or c, tp x are referenced to v tpu pin (pin 9). 3. v cc = v rst (max) to 3.6v ai11147b sal t h temperature t hyst(high) t hyst(low) t l
stm1404 package mechanical data 31/36 package mechanical data figure 29. qfn16 ? 16-lead, quad, flat package, no lead, 3x3mm body size, outline note: drawing is not to scale. a3 a a1 e k k b ch d2 e2 l e d 1 2 ddd 3 qfn16-a c
package mechanical data stm1404 32/36 figure 30. qfn16 ? 16-lead, quad, flat package, no lead, 3x3mm, recommended footprint note: substrate pad should be tied to v ss . table 8. qfn16 ? 16-lead, quad, flat package, no lead, 3x3mm body size mechanical data symb mm inches typ min max typ min max a 0.90 0.80 1.00 0.035 0.032 0.039 a1 0.02 0.00 0.05 0.001 0.000 0.002 a3 0.20 ? ? 0.008 ? ? b 0.25 0.18 0.30 0.010 0.007 0.012 d 3.00 2.90 3.10 0.118 0.114 0.122 d2 1.70 1.55 1.80 0.067 0.061 0.071 e 3.00 2.90 3.10 0.118 0.114 0.122 e2 1.70 1.55 1.80 0.067 0.061 0.071 e0.50? ?0.020? ? k 0.20 ? ? 0.008 ? ? l 0.40 0.30 0.50 0.016 0.012 0.020 ddd ? 0.08 ? ? 0.003 ? ch ?0.33? ?0.013? n16 16 0.28 1.60 3.55 2.0 ai09126
stm1404 part numbering 33/36 part numbering table 9. ordering information scheme (see figure 31 on page 34 for marking information) for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. example: stm1404 a t m d q 6 f device type stm1404: over/under temperature detect v out status (sal = active-low) a: v out = on; vccsw = normal mode b (1) : v out = high-z; vccsw = high 1. contact local st sales office for availability. c: v out = ground; vccsw = high reset threshold voltage t: v rst = 3.00v to 3.15v s: v rst = 2.85v to 3.00v r: v rst = 2.55v to 2.70v battery low voltage detect threshold (v det ) m: v det = 2.3v (typ) n: v det = 2.5v (typ) o: v det = 3.2v (typ) under (tl)/over (th) temperature alarm thresholds (stm1404 only) b: ?25/+80c h: ?35/+80c c: ?25/+85c i: ?35/+85c d: ?25/+95c j: ?35/+95c package q = qfn16 (3mm x 3mm) temperature range 6 = ?40 to 85c shipping method f = ecopack package, tape & reel
part numbering stm1404 34/36 figure 31. topside marking information 1. options codes: x = a, b, or c (for v out ) x = t, s, or r (for reset threshold) x = m, n, or o (for battery low voltage detect threshold) x = b, c, d, h, i, or j (for temperature alarm threshold) 2. traceability codes y = year ww = work week 04 xxxx (1) yww (2) ai12218
stm1404 revision history 35/36 revision history table 10. document revision history date version description 11-oct-2004 1.0 first edition 26-nov-2004 1.1 corrected footprint dimensions; update characteristics (figure 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 26 , 27 , 30 and table 1 , 2 , 3 , 6 , 7 ). 22-dec-2004 1.2 update characteristics ( figure 4 , tables 6 , 7 , 9 ). 03-feb-2005 1.3 update characteristics ( figure 4 , tables 6 , 7 ). 25-feb-2005 1.4 update temperature trip limits ( ta b l e 9 ) 06-may-2005 1.5 update characteristics (figure 3 , 4 , 28 and table 6 , 7 ). 05-aug-2005 2.0 removed stm1403 references (figure 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 26 , 27 , 28 and table 1 , 2 , 5 , 6 , 7 , 9 ). 06-jan-2006 3.0 update status, characteristics, lead-free text, marking (figure 4 , 31 and ta b l e 6 , 7 , 9 ). 08-feb-2007 4.0 update cover page, figure 3: block diagram , table 7: physical and environmental tamper detection levels , figure 28: temperature hysteresis , and part numbering ( table 9. )
stm1404 36/36 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2007 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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